(1) Field of the Invention
The present invention relates to the field of video display systems. More specifically, the present invention relates circuits for synchronizing the video signals from one or more devices.
(2) Prior Art
Multiple video devices are often used together as video sources to produce a resultant video image. One of the video devices can be a graphics computer. Alternatively, one of the video devices can also be any sort of recorded multi-media player, e.g., a CD-ROM player, etc. In linking the video devices, the video devices are required to be synchronized with each other. In most of the video/graphics systems, the devices need to be synchronized together in terms of the vertical and horizontal signal frequencies. Specifically, the signal from one device needs to line up with the signal from the other device for proper video linking.
A synchronizing device, which can reside in one of the video devices, is used for the synchronization. The synchronizing device analyzes the reference synchronization (sync) signal from the other video devices. In order to properly synchronize different video devices, e.g., the output of a graphics computer to the output of a video studio sync signal, every synchronizing device needs to analyze the reference sync signal generated by a video reference device. At a minimum, the devices should be synchronized vertically to maintain the same vertical rate and vertical phase. To synchronize vertically, the synchronizing device needs to ascertain the start of the frame from the video reference signal (of the video signal) using a frame detector. This video reference signal is also called the composite sync signal and is a train of pulses of different widths as well as different time intervals between the pulses. In this composite signal, there are pulses marking the start of the horizontal lines and a number of pulses of different duration and time between them are used for marking the start of the video frame and fields. The start of frame information is used to synchronize the video signals.
One prior art synchronizing device detects the start of a frame by looking for serration pulses after the equalization pulse. However, this prior art device is "hard wired" and only accepts a limited number of video formats. For all "hard wired" start of frame detectors, when new video formats are developed, the prior art synchronizing device is unable to handle the new format because it is not adaptable. For each new video format, new circuitry is made and a new synchronizing device needs to be developed. For instance, certain circuits of this prior art technique are designed for recognizing only NTSC and PAL formats. Using this approach, for a single synchronization circuit to handle multiple video formats, the circuit needs to contain many sub-circuits with each sub-circuit being custom built for a particular video signal format. This prior art technique for performing video synchronizing leads is a very costly and complex solution.
Another prior art synchronizing device is described in U.S. Pat. No. 5,608,461 issued on Mar. 4, 1997 by G. Sadowski, et al., and includes a programmable mechanism whereby known signal patterns can be manually programmed into a memory. Within the programmable mechanism, the synchronization circuit can be programmed to recognize the start of frame signal for a given video format. Although this prior art mechanism is more robust compared to the "hard wired" design described above, it nevertheless requires that the synchronization circuit be manually programmed to recognize each new video format. Programming typically requires manual attention to the video equipment which requires a good deal of computer hardware and software support to implement and maintain. This approach is also error prone, can be costly over time and can result in unnecessary intrusion into the video equipment.
A variety of video formats do exist in the video technology arena and the encoding technique of the start of frame in the composite sync signal is different from one video format to another. Further, it is expected that over time a variety of new video formats will be developed, each having different start frame encoding techniques. At the same time, it would be desirable to have just one circuit capable of providing signal synchronization for all of the video formats without requiring programming each time a new video format or standard is made available.
Accordingly, the present invention offers a video frame detector circuit that is capable of providing synchronization for a variety of video signal formats without requiring programming a priori. These and other advantageous of the present invention not specifically described above will become clear within discussions of the present invention herein.